The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device including a plurality of devices mounted on a lead frame.
A semiconductor device including one or more semiconductor chips mounted on one face of a die pad of a lead frame and encapsulated with a resin is widely used. As a first example of typical semiconductor devices currently used, FIGS. 5A through 5C show the structure of a 14-pin SOP (Small Outline Package) disclosed in Japanese Laid-Open Patent Publication No. 8-279590. FIG. 5A is a plan view of the semiconductor device, FIG. 5B is a side view thereof and FIG. 5C is a cross-sectional view thereof taken along line A–A′ of FIG. 5A.
As shown in FIGS. 5A through 5C, a bare chip 102 is disposed on a die pad 101, and the bare chip 102 is connected to a lead 107 through a bonding wire 106 to be electrically connected to an external circuit. A base body including the die pad 101, the bare chip 102 and the lead 107 is encapsulated with a package mold 108.
Also, as a second example, FIGS. 6A and 6B show the cross-sectional structure of a semiconductor device including a plurality of semiconductor chips that is disclosed in Japanese Laid-Open Patent Publication No. 8-279590. FIGS. 6A and 6B respectively show the cross-sections taken in different positions. As shown in FIGS. 6A and 6B, a first bare chip 102 is mounted on the top face of a die pad 101 and a second bare chip 202 is mounted on the reverse face of the die pad 101. The bare chips 102 and 202 are identical to each other. The first bare chip 102 is connected, through bonding wires 106, to inner lead portions 107a of leads 107 included in the same lead frame as the die pad 101. The second bare chip 202 is connected, through bonding wires 206, to inner lead portions 207a of leads 207 included in a second lead frame disposed below the die pad 101. These elements are encapsulated with a package mold 108.
In the first example of the conventional semiconductor devices in which a semiconductor chip is mounted on one face of a die pad, the number of semiconductor chips that can be formed within one package is one, and therefore, the degree of integration within the semiconductor device is low.
On the other hand, in the second example shown in FIGS. 6A and 6B, since semiconductor chips are mounted on both the top and reverse faces of a die pad of one lead frame, the degree of integration within the semiconductor device can be increased. However, it is necessary to perform, on both the top and reverse faces of one lead frame, chip mounting processing for mounting the semiconductor chips on the lead frame and wire bonding processing for connecting electrodes of the semiconductor chips to inner lead portions through metal wires. Therefore, the fabrication process is disadvantageously complicated. For example, when one semiconductor chip is assembled after assembling another semiconductor chip, the previously assembled semiconductor chip is pressed, which can be a factor to cause assembly defective. In order to overcome this problem of assembly defective, special assembly facilities are disadvantageously necessary.
Also, when a semiconductor chip is mounted on each of the two faces of one lead frame, the thickness of the resultant package is large, and hence, a large packaging space for the thick package is necessary. This is not suitable to high-density packaging of electronic equipment.